As the physical size of semiconductor devices, such as transistors, continues to decrease with each new generation of integrated circuit (IC) fabrication technology, consequences of these smaller sizes create new challenges that designers and fabricators must overcome to make the ICs functional. In the field of MOSFETs (metallic oxide semiconductor field effect transistors), which are some of the most common semiconductor devices used today, the decrease in size and commensurate decrease in operating current have led to current leakage becoming problematic when the transistor is in its off state. This leakage is caused by, among other things, parasitic devices that form in the substrate beneath the gate of the FET. Generally, a parasitic device is, among other things, a pathway for current to flow when and/or where such current flow is not desired. Parasitic devices are typically caused by imperfect fabrication and other physical limitations. In conventional planar CMOS technology wherein FETs are formed on a full-thickness silicon wafer, a primary parasitic device can form in the channel between the source and drain beyond a certain depth beneath the gate where the gate's field is no longer effective.
One solution to this current leakage problem for planar FETs is to provide a second gate beneath the channel (such FETs are known as dual gate FETs, or DG FETs). The second gate generally provides two functions: it 1) provides a lower boundary for the channel and 2) provides a second field for regulating the current flow through the channel. While DG MOSFETs have definite advantages over single gate MOSFETs, they have some drawbacks. These drawbacks include relative difficulty in forming the lower gate and difficulty in properly aligning the two gates one above the other.
Relatively recently, a new sort of DG MOSFET has been introduced in conjunction with silicon on insulator (SOI) technology that overcomes some of the drawbacks of planar DG MOSFETs. As seen in FIG. 1A, this new DG MOSFET 10 is formed vertically rather than horizontally and has been given the name finFET, since the structure 12 that contains each pair of source 14 and drain 18 resembles a fin. As mentioned, finFET 10 is typically made using a SOI wafer 22 that includes a buried oxide (BOX) layer 26 sandwiched between a silicon lower layer 30 and a silicon upper layer 34. In the case of finFET 10, much of upper layer 34 has been etched away to define two parallel fins 12 that each form one source 14, one drain 18 and a channel 42 (FIG. 1B) between the source and drain. After fins 12 have been formed, subsequent processing steps include forming a gate oxide (not shown) on fins 12 and forming gate 46, which is common to both fins. Once gate 46 has been formed, sources 14 and drains 18 are doped, as illustrated by arrows 50, to achieve the proper doping. Doping is typically done using ion implantation from the front side of wafer 22, typically at an angle of about 30 degrees relative to a normal from the wafer so that ions can enter each fin 12 along its entire height without interference from an adjacent fin.
In FIG. 1A it is readily seen that finFET 10 avoids the problem in planar CMOS technology of having to form a second gate beneath the channel of the FET. FinFET 10 also overcomes the problem in planar CMOS technology of having to align gates above and below the channel. Since fins 12 are free-standing structures prior to the formation of gate 46, the portions of the gate on either side of each channel 42 (FIG. 1B) are largely self-aligned as a result of forming the gate perpendicular to the fins.
Although finFETs overcome some of the fabrication challenges of comparable planar CMOSFETs, they presently have several drawbacks that are essentially artifacts of the fabrication process. Referring to FIG. 1B, one of these drawbacks is the formation of a parasitic device 54 adjacent the top of channel 42. Parasitic device 54, when present, is typically an artifact of the processes of removing the hardmask 56 needed to form fins 12 subsequent to the formation of gate 46 and doping source 14 and drain 18. After gate 46 is formed, hardmask 56 is typically removed from the portions of each fin 12 not underneath the gate using a dilute hydrofluoric acid etch. However, this etch is isotropic, so that when hardmask 56 is removed, portions of the hardmask and/or the gate oxide layer (not shown) under gate 46 adjacent the lateral sides of the gate are etched so as to undercut the portion of the gate above each fin 12. During doping of source 14 and drain 18, the upper region of fin 12 out from underneath gate 46 receives additional doping due its exposure to the ion implantation doping of the source and drain during the doping of both sides of the fin (see FIG. 1A, arrows 50). This additional doping causes the concentration of dopant atoms adjacent to the top of source 14 and drain 18 to generally be higher than the doping in other regions of the source and drain. Consequently, this higher doping results in greater lateral diffusion of dopant atoms into channel 42 at the upper portion of the channel. This is illustrated by doping profiles 58 that represent the extent of diffusion of dopant atoms into channel 42. The presence of source and drain dopant atoms at these locations causes the effective length to be shorter in this region of channel 42, thereby creating parasitic device 54 that can interfere with the desired flow of current through the channel. In addition, since hardmask 56 is no longer present at the undercut regions of gate 46, dopant atom can enter into each fin 12 at these undercut regions, thereby causing dopant atoms to be implanted relatively far into channel 42 relative to the lateral sides of gate 46. These additional dopant atoms further interfere with the desired current flow characteristics of channel 42.
Another drawback of present finFETs that is also an artifact of fabrication, is the formation of corner-type parasitic devices at the bottoms of sources and drains. These parasitic devices are the result of the BOX layer being pulled down and undercut (see FIG. 7 element no. 144) at the bottoms of each source and drain. This undercutting is due to other steps in the formation of the finFET, such as the wet etch step used to remove residue polymers left behind by the etching of a gate, which is typically polysilicon.